400G-Per-Lane SerDes PHY
Our first product targets 400 Gb/s per electrical lane while retaining the current field-proven channel and analog architecture.
CODING-DRIVEN HIGH-SPEED SERDES
400G SerDes PHY for AI data center interconnect fabric.
Linxcale is developing a coding-driven 400G-per-lane electrical SerDes PHY as the foundation for low-latency switching and memory-centric AI data center fabric.
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WHAT WE DO
From coding-driven SerDes PHY to scalable AI data center fabric.
Coding-Driven PHY
PAM8 increases bits per symbol while advanced FEC and coded modulation recover SNR margin, targeting higher throughput without wider electrical channels.
AI Data Center Fabric
Built on our SerDes PHY, the fabric roadmap combines low-latency switching with memory-centric connectivity for scale-up and scale-out AI systems.
LINXCALE TECHNOLOGY
From SerDes PHY to AI data center fabric.
Linxcale is a California semiconductor technology company combining communications coding expertise with production SerDes analog design. Starting with a 400G-per-lane PHY, our roadmap expands into low-latency switching and memory-centric fabric, with a path toward 800G and 1.6T interconnects.
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